GBE: Support 64Bit register spill

Graphics / Beignet - Ruiling Song [intel.com] - 14 February 2014 01:06 UTC

Now we support DWORD & QWORD register spill/fill.

v2: only add poolOffset by 1 when we meet QWord register and poolOffset is 1.

v3: allocate reserved register pool unifiedly for src and dst register. when it spill a qword register, payload register should be retyped as dword per bottom/top logic. put a limit on the scratch space memory size.

v4: fix a typo. increase the reserved register from 6 to 8 for some complex instruction.

5362669 GBE: Support 64Bit register spill.
backend/src/backend/gen_context.cpp | 45 ++++++++++++++++++----
backend/src/backend/gen_insn_selection.cpp | 56 +++++++++++++++-------------
backend/src/backend/gen_reg_allocation.cpp | 18 +++++----
backend/src/backend/gen_reg_allocation.hpp | 1 +
src/cl_command_queue_gen7.c | 3 +-
5 files changed, 82 insertions(+), 41 deletions(-)

Upstream: cgit.freedesktop.org

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