AGESA: Add romstage timestamps

Hardware / Coreboot - Kyösti Mälkki [gmail.com] - 2 August 2017 00:51 EDT

Experiments on f14 f15tn and 16kb suggest that TSC counter value shifts at end of raminit. To account for this all previously stored values in timestamp table are also divided by 4.

Change-Id: I47584997bf456e35cf0aeb97ef255748745c30ee

7369e83 AGESA: Add romstage timestamps
src/cpu/amd/agesa/romstage.c | 10 ++++++++++
1 file changed, 10 insertions(+)

Upstream: review.coreboot.org


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