intel/apollolake: Add soc specific DPTF values

Hardware / Coreboot - Shaunak Saha [intel.com] - 28 July 2016 13:10 UTC

This patch adds apollolake soc specific change. DPTF ASL files are now in src/soc/intel/common so that they can be reused but different soc can have different values e.g., for skylake cpu soc thermal reporting device is at Bus 0, Device 4, Function 0 while for apollolake it is Bus 0, Device 0, Function 1. This patch adds a dptf asl file in soc directory where we can define all values which can change across soc's and can be included in mainboard dptf asl.

BUG=chrome-os-partner:53096 TEST=In Amenia and Reef board verify that the thermal zones are enumerated under /sys/class/thermal in Amenia and Reef board. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there.

Change-Id: I888260a9c799d36512411a769f26dd30cf8d5788

5dd2b18 intel/apollolake: Add soc specific DPTF values
src/soc/intel/apollolake/acpi/dptf.asl | 44 ++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)

Upstream: review.coreboot.org

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