intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP

Hardware / Coreboot - York Yang [intel.com] - 31 January 2015 16:09 UTC

Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change.

PcdCustomerRevision is a debugging aid that will be output to debug message in FSP. When needed, it can be customized by BCT tool for tracking BCT configurations.

Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b

e1e11e6 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
src/northbridge/intel/fsp_rangeley/chip.h | 10 ++++++++++
.../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 7 +++++++
src/vendorcode/intel/fsp/rangeley/include/fspvpd.h | 15 ++++++++++-----
3 files changed, 27 insertions(+), 5 deletions(-)

Upstream: review.coreboot.org

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