riscv: add support to block smp in each stage

Hardware / Coreboot - Xiang Wang [126.com] - 5 November 2018 09:03 EST

Each stage performs some basic initialization (stack, HLS etc) and then call smp_pause to enter the single-threaded state. The main work of each stage is executed in a single-threaded state, and the multi-threaded state is restored by call smp_resume while booting the next stage.

Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee

26f725efc2 riscv: add support to block smp in each stage
src/arch/riscv/boot.c | 8 +++++++-
src/arch/riscv/bootblock.S | 10 +++-------
src/arch/riscv/ramstage.S | 3 +++
src/arch/riscv/stages.c | 3 +++
4 files changed, 16 insertions(+), 8 deletions(-)

Upstream: review.coreboot.org


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