riscv: add trampoline in MBR block to support boot mode 1

Hardware / Coreboot - Philipp Hug [hug.cx] - 14 September 2018 14:33 EDT

Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock.

Tested on hardware: boot mode 15: works as before boot mode 1: jump to bootblock works, but bootblock needs to be modified to move the stack to L2LIM. This will be in a separate commit.

Further changes are needed in the bootblock

Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86

2326a284ac riscv: add trampoline in MBR block to support boot mode 1
Documentation/mainboard/sifive/hifive-unleashed.md | 2 +-
util/riscv/sifive-gpt.py | 14 +++++++++++++-
2 files changed, 14 insertions(+), 2 deletions(-)

Upstream: review.coreboot.org


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