riscv: enable counters via m[us]counteren

Hardware / Coreboot - Ronald G. Minnich [gmail.com] - 19 December 2016 18:10 EST

The user and supervisor counters could not be safely enabled before as the register numbers were not finalized. Now that everyone agrees, we can enable them. Until we are sure the toolchains are caught up, we use the hardcode name with the register names in comments. As soon as toolchains settle down we'll do one more pass and convert to the symbolic names.

Tested on lowrisc bitstream and SPIKE simulator.

Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6

f171e66 riscv: enable counters via m[us]counteren
src/arch/riscv/virtual_memory.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)

Upstream: review.coreboot.org


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