riscv: update misaligned memory access exception handling

Hardware / Coreboot - Xiang Wang [126.com] - 10 September 2018 15:03 EDT

Support for more situations: floating point, compressed instructions, etc. Add support for redirect exception to S-Mode.


Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f

cda59b56ba riscv: update misaligned memory access exception handling
src/arch/riscv/Makefile.inc | 4 +
src/arch/riscv/fp_asm.S | 362 ++++++++++++++++++++++++++++++++
src/arch/riscv/include/arch/exception.h | 11 +-
src/arch/riscv/misaligned.c | 267 +++++++++++++++++++++++
src/arch/riscv/trap_handler.c | 76 ++-----
5 files changed, 652 insertions(+), 68 deletions(-)

Upstream: review.coreboot.org


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