riscv: Unify SBI call implementations under arch/riscv/

Hardware / Coreboot - Jonathan Neuschäfer [gmx.net] - 7 November 2016 09:47 UTC

Note that currently, traps are only handled by the trap handler installed in the bootblock. The romstage and ramstage don't override it.

TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux payload. It worked as much as before (Linux didn't boot, but it made some successful SBI calls)

Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e

99f2f11 riscv: Unify SBI call implementations under arch/riscv/
src/arch/riscv/Makefile.inc | 2 +-
src/arch/riscv/include/mcall.h | 70 +++++++++++++++
src/arch/riscv/include/spike_util.h | 70 ---------------
src/arch/riscv/mcall.c | 101 +++++++++++++++++++++
src/arch/riscv/trap_handler.c | 2 +-
src/mainboard/emulation/qemu-riscv/Makefile.inc | 3 -
src/mainboard/emulation/qemu-riscv/qemu_util.c | 100 ---------------------
src/mainboard/emulation/spike-riscv/Makefile.inc | 3 -
src/mainboard/emulation/spike-riscv/spike_util.c | 100 ---------------------
src/mainboard/emulation/spike-riscv/uart.c | 1 -
src/mainboard/lowrisc/nexys4ddr/Makefile.inc | 3 -
src/mainboard/lowrisc/nexys4ddr/uart.c | 1 -
src/mainboard/lowrisc/nexys4ddr/util.c | 103 ----------------------
13 files changed, 173 insertions(+), 386 deletions(-)

Upstream: review.coreboot.org

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