Bounce buffers used to be used in those cases where the payload might overlap coreboot.
Bounce buffers are a problem for rampayloads as they need malloc.
They are also an artifact of our x86 past before we had relocatable ramstage; only x86, out of the 5 architectures we support, needs them; currently they only seem to matter on the following chipsets: src/northbridge/amd/amdfam10/Kconfig src/northbridge/amd/lx/Kconfig src/northbridge/via/vx900/Kconfig src/soc/intel/fsp_baytrail/Kconfig src/soc/intel/fsp_broadwell_de/Kconfig
The first three are obsolete or at least could be changed to avoid the need to have bounce buffers. The last two should change to no longer need them. In any event they can be fixed or pegged to a release which supports them.
For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the
value needed in 1999 for the 32-bit Linux kernel, the original ramstage) to 0xe00000 (14 Mib) which will put the non-relocatable x86 ramstage out of the way of any reasonable payload until we can get rid of it for good.
14 MiB was chosen after some discussion, but it does fit well: o Fits in the 16 MiB cacheable range coreboot sets up by default o Most small payloads are well under 14 MiB (even kernels!) o Most large payloads get loaded at 16 MiB (especially kernels!)
With this change in place coreboot correctly still loads a bzImage payload.
Werner reports that the 0xe00000 setting works on his broadwell systems.
83bd46e5e5 selfboot: remove bounce buffers
src/arch/arm/boot.c | 5 -
src/arch/arm64/boot.c | 5 -
src/arch/mips/boot.c | 5 -
src/arch/power8/boot.c | 5 -
src/arch/riscv/boot.c | 5 -
src/arch/x86/Kconfig | 11 +-
src/arch/x86/boot.c | 201 ------------
src/include/bootmem.h | 5 -
src/include/program_loading.h | 3 -
src/lib/bootmem.c | 9 -
src/lib/selfboot.c | 537 +++++++--------------------------
src/northbridge/amd/amdfam10/Kconfig | 4 -
src/soc/intel/fsp_broadwell_de/Kconfig | 4 -
13 files changed, 124 insertions(+), 675 deletions(-)