soc/intel/common: Add function to protect MRC cache

Hardware / Coreboot - Duncan Laurie [chromium.org] - 18 April 2015 01:43 UTC

Add support for applying write protection to the MRC cache region in SPI flash.

This is only enabled if there is write protect GPIO that is set, and the flash status register reports that the flash chip is currently write protected.

Then it will call out to a SOC specific function that will enable write protection on the RW_MRC_CACHE region of flash.

The implementation is not quite as clean as I would like because there is not a common flash protect interface across SOCs so instead it relies on a new Kconfig variable to be set that will indicate a SOC implements the function to protect a region of SPI flash.

BUG=chrome-os-partner:28234 BRANCH=broadwell TEST=build and boot on samus 1) with either WPSW=0 or SRP0=0 the PRR is not applied 2) with both WPSW=1 and SRP0=1 the PRR is applied

Change-Id: If5907b7ddf3f966c546ae32dc99aa815beb27587

a32b6b9 soc/intel/common: Add function to protect MRC cache
src/soc/intel/common/Kconfig | 4 ++++
src/soc/intel/common/mrc_cache.c | 21 ++++++++++++++++++
src/soc/intel/common/nvm.c | 44 ++++++++++++++++++++++++++++++++++++++
src/soc/intel/common/nvm.h | 6 ++++++
4 files changed, 75 insertions(+)

Upstream: review.coreboot.org


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