soc/intel/common: Enable support to write protect SPI flash range

Hardware / Coreboot - Furquan Shaikh [chromium.org] - 25 October 2016 18:50 UTC

Write-protect SPI flash range provided by caller by using a free Flash Protected Range (FPR) register. This expects SoC to define a callback for providing information about the first FPR register address and maximum number of FPRs supported.

BUG=chrome-os-partner:58896

Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add

aedbfc8 soc/intel/common: Enable support to write protect SPI flash range
src/soc/intel/common/Kconfig | 4 +++
src/soc/intel/common/Makefile.inc | 1 +
src/soc/intel/common/nvm.c | 2 +-
src/soc/intel/common/spi.c | 66 +++++++++++++++++++++++++++++++++++++
src/soc/intel/common/spi.h | 45 +++++++++++++++++++++++++
5 files changed, 117 insertions(+), 1 deletion(-)

Upstream: review.coreboot.org

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