[AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

Programming / Compilers / GCC - ktkachov [138bc75d-0d04-0410-961f-82ee72b054a4] - 25 September 2019 12:38 EDT

The DCache clean & ICache invalidation requirements for instructions to be data coherence are discoverable through new fields in CTR_EL0. Let's support the two bits if they are enabled, the CPU core will not execute the unnecessary DCache clean or Icache Invalidation instructions.

2019-09-25 Shaokun Zhang

- config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Add support for CTR_EL0.IDC and CTR_EL0.DIC.

164c7d29912 [AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC
libgcc/ChangeLog | 5 ++++
libgcc/config/aarch64/sync-cache.c | 57 ++++++++++++++++++++++++--------------
2 files changed, 41 insertions(+), 21 deletions(-)

Upstream: gcc.gnu.org


  • Share