tlsdesc calls are guaranteed to preserve all Advanced SIMD registers, but are not guaranteed to preserve the SVE extension of them. The calls also don't preserve the SVE predicate registers.
The long-term plan for handling the SVE vector registers is CLOBBER_HIGH, which adds a clobber equivalent of TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The pattern can then directly model the fact that the low 128 bits are preserved and the upper bits are clobbered.
However, it's too late now for that to be included in GCC 8, so this patch conservatively treats the whole vector register as being clobbered. This has the obvious disadvantage that compiling for SVE can make NEON code worse, but I don't think there's much we can do about that until CLOBBER_HIGH is in.
2018-03-13 Richard Sandiford
- config/aarch64/aarch64.md (V4_REGNUM, V8_REGNUM, V12_REGNUM) (V20_REGNUM, V24_REGNUM, V28_REGNUM, P1_REGNUM, P2_REGNUM, P3_REGNUM) (P4_REGNUM, P5_REGNUM, P6_REGNUM, P8_REGNUM, P9_REGNUM, P10_REGNUM) (P11_REGNUM, P12_REGNUM, P13_REGNUM, P14_REGNUM): New define_constants. (tlsdesc_small_
- gcc.target/aarch64/sve/tls_1.c: New test.
- gcc.target/aarch64/sve/tls_2.C: Likewise.
62b3b99903c [AArch64] Add a tlsdesc call pattern for SVE
gcc/ChangeLog | 11 ++++
gcc/config/aarch64/aarch64.md | 80 ++++++++++++++++++++++++++--
gcc/testsuite/ChangeLog | 5 ++
gcc/testsuite/gcc.target/aarch64/sve/tls_1.c | 17 ++++++
gcc/testsuite/gcc.target/aarch64/sve/tls_2.C | 30 +++++++++++
5 files changed, 140 insertions(+), 3 deletions(-)