[AArch64] Add autovec support for partial SVE vectors

Programming / Compilers / GCC - rsandifo [138bc75d-0d04-0410-961f-82ee72b054a4] - 16 November 2019 11:02 EST

This patch adds the bare minimum needed to support autovectorisation of partial SVE vectors, namely moves and integer addition. Later patches add more interesting cases.

2019-11-16 Richard Sandiford

gcc/
- config/aarch64/aarch64-modes.def: Define partial SVE vector float modes.
- config/aarch64/aarch64-protos.h (aarch64_sve_pred_mode): New function.
- config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle the new vector float modes. (aarch64_sve_container_bits): New function. (aarch64_sve_pred_mode): Likewise. (aarch64_get_mask_mode): Use it. (aarch64_sve_element_int_mode): Handle structure modes and partial modes. (aarch64_sve_container_int_mode): New function. (aarch64_vectorize_related_mode): Return SVE modes when given SVE modes. Handle partial modes, taking the preferred number of units from the size of the given mode. (aarch64_hard_regno_mode_ok): Allow partial modes to be stored in registers. (aarch64_expand_sve_ld1rq): Use the mode form of aarch64_sve_pred_mode. (aarch64_expand_sve_const_vector): Handle partial SVE vectors. (aarch64_split_sve_subreg_move): Use the mode form of aarch64_sve_pred_mode. (aarch64_secondary_reload): Handle partial modes in the same way as full big-endian vectors. (aarch64_vector_mode_supported_p): Allow partial SVE vectors. (aarch64_autovectorize_vector_modes): Try unpacked SVE vectors, merging with the Advanced SIMD modes. If two modes have the same size, try the Advanced SIMD mode first. (aarch64_simd_valid_immediate): Use the container rather than the element mode for INDEX constants. (aarch64_simd_vector_alignment): Make the alignment of partial SVE vector modes the same as their minimum size. (aarch64_evpc_sel): Use the mode form of aarch64_sve_pred_mode.
- config/aarch64/aarch64-sve.md (mov): Extend to... (mov): ...this. (movmisalign): Extend to... (movmisalign): ...this. (*aarch64_sve_mov_le): Rename to... (*aarch64_sve_mov_ldr_str): ...this. (*aarch64_sve_mov_be): Rename and extend to... (*aarch64_sve_mov_no_ldr_str): ...this. Handle partial modes regardless of endianness. (aarch64_sve_reload_be): Rename to... (aarch64_sve_reload_mem): ...this and enable for little-endian. Use aarch64_sve_pred_mode to get the appropriate predicate mode. (@aarch64_pred_mov): Extend to... (@aarch64_pred_mov): ...this. (*aarch64_sve_mov_subreg_be): Extend to... (*aarch64_sve_mov_subreg_be): ...this. (@aarch64_sve_reinterpret): Extend to... (@aarch64_sve_reinterpret): ...this. (*aarch64_sve_reinterpret): Extend to... (*aarch64_sve_reinterpret): ...this. (maskload): Extend to... (maskload): ...this. (maskstore): Extend to... (maskstore): ...this. (vec_duplicate): Extend to... (vec_duplicate): ...this. (*vec_duplicate_reg): Extend to... (*vec_duplicate_reg): ...this. (sve_ld1r): Extend to... (sve_ld1r): ...this. (vec_series): Extend to... (vec_series): ...this. (*vec_series_plus): Extend to... (*vec_series_plus): ...this. (@aarch64_pred_sxt): Avoid new VPRED ambiguity. (@aarch64_cond_sxt): Likewise. (add3): Extend to... (add3): ...this.
- config/aarch64/iterators.md (SVE_ALL, SVE_I): New mode iterators. (Vetype, Vesize, VEL, Vel, vwcore): Handle partial SVE vector modes. (VPRED, vpred): Likewise. (Vctype): New iterator. (vw): Remove SVE modes.

gcc/testsuite/
- gcc.target/aarch64/sve/mixed_size_1.c: New test.
- gcc.target/aarch64/sve/mixed_size_2.c: Likewise.
- gcc.target/aarch64/sve/mixed_size_3.c: Likewise.
- gcc.target/aarch64/sve/mixed_size_4.c: Likewise.
- gcc.target/aarch64/sve/mixed_size_5.c: Likewise.

d2d250a0d08 [AArch64] Add autovec support for partial SVE vectors
gcc/ChangeLog | 79 +++++++
gcc/config/aarch64/aarch64-modes.def | 8 +
gcc/config/aarch64/aarch64-protos.h | 1 +
gcc/config/aarch64/aarch64-sve.md | 133 ++++++------
gcc/config/aarch64/aarch64.c | 230 +++++++++++++++++----
gcc/config/aarch64/iterators.md | 176 +++++++++++-----
gcc/testsuite/ChangeLog | 8 +
.../gcc.target/aarch64/sve/mixed_size_1.c | 39 ++++
.../gcc.target/aarch64/sve/mixed_size_2.c | 41 ++++
.../gcc.target/aarch64/sve/mixed_size_3.c | 41 ++++
.../gcc.target/aarch64/sve/mixed_size_4.c | 43 ++++
.../gcc.target/aarch64/sve/mixed_size_5.c | 42 ++++
12 files changed, 674 insertions(+), 167 deletions(-)

Upstream: gcc.gnu.org


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