This patch adds extra vector modes that represent a half, quarter or eighth of what an SVE vector can hold. This is useful for describing the memory vector involved in an extending load or truncating store. It might also be useful in future for representing "unpacked" SVE registers, i.e. registers that contain values in the low bits of a wider containing element.
The new modes could have the same width as an Advanced SIMD mode for certain -msve-vector-bits=N options, so we need to ensure that they come later in the mode list and that Advanced SIMD modes always "win".
2019-10-16 Richard Sandiford
- genmodes.c (mode_data::order): New field. (blank_mode): Update accordingly. (VECTOR_MODES_WITH_PREFIX): Add an order parameter. (make_vector_modes): Likewise. (VECTOR_MODES): Update use accordingly. (cmp_modes): Sort by the new order field ahead of sorting by size.
- config/aarch64/aarch64-modes.def (VNx2QI, VN2xHI, VNx2SI) (VNx4QI, VNx4HI, VNx8QI): New partial vector modes.
- config/aarch64/aarch64.c (VEC_PARTIAL): New flag value. (aarch64_classify_vector_mode): Handle the new partial modes. (aarch64_vl_bytes): New function. (aarch64_hard_regno_nregs): Use it instead of BYTES_PER_SVE_VECTOR when counting the number of registers in an SVE mode. (aarch64_class_max_nregs): Likewise. (aarch64_hard_regno_mode_ok): Don't allow partial vectors in registers yet. (aarch64_classify_address): Treat partial vectors analogously to full vectors. (aarch64_print_address_internal): Consolidate the printing of MUL VL addresses, using aarch64_vl_bytes as the number of bytes represented by "VL". (aarch64_vector_mode_supported_p): Reject partial vector modes.
e4c0abf18da [AArch64] Add partial SVE vector modes
gcc/ChangeLog | 25 ++++++++++
gcc/config/aarch64/aarch64-modes.def | 38 ++++++++++++++-
gcc/config/aarch64/aarch64.c | 92 ++++++++++++++++++++++++++----------
gcc/genmodes.c | 22 ++++++---
4 files changed, 144 insertions(+), 33 deletions(-)