[AArch64] Remove use of wider vector modes

Programming / Compilers / GCC - rsandifo [138bc75d-0d04-0410-961f-82ee72b054a4] - 31 August 2017 05:51 EDT

The AArch64 port defined x2, x3 and x4 vector modes that were only used in the rtl for the AdvSIMD LD{2,3,4} patterns. It seems unlikely that this rtl would have led to any valid simplifications, since the values involved were unspecs that had a different number of operands from the non-dreg versions. (The dreg UNSPEC_LD2 had a single operand, while the qreg one had two operands.)

As it happened, the patterns led to invalid simplifications on big-endian targets due to a mix-up in the operand order, see Tamar's fix in r240271.

This patch therefore replaces the rtl patterns with dedicated unspecs. This allows the x2, x3 and x4 modes to be removed, avoiding a clash with 256-bit and 512-bit SVE.

2017-08-22 Richard Sandiford Alan Hayward David Sherwood

gcc/
- config/aarch64/aarch64-modes.def: Remove 32-, 48- and 64-byte
vector modes.
- config/aarch64/iterators.md (VRL2, VRL3, VRL4): Delete.
- config/aarch64/aarch64.md (UNSPEC_LD2_DREG, UNSPEC_LD3_DREG) (UNSPEC_LD4_DREG): New unspecs.
- config/aarch64/aarch64-simd.md (aarch64_ld2_dreg_le) (aarch64_ld2_dreg_be): Replace with... (aarch64_ld2_dreg): ...this pattern and use the new DREG unspec. (aarch64_ld3_dreg_le) (aarch64_ld3_dreg_be): Replace with... (aarch64_ld3_dreg): ...this pattern and use the new DREG unspec. (aarch64_ld4_dreg_le) (aarch64_ld4_dreg_be): Replace with... (aarch64_ld4_dreg): ...this pattern and use the new DREG unspec.

0444c2e [AArch64] Remove use of wider vector modes
gcc/ChangeLog | 22 +++
gcc/config/aarch64/aarch64-modes.def | 10 --
gcc/config/aarch64/aarch64-simd.md | 283 ++++-------------------------------
gcc/config/aarch64/aarch64.md | 3 +
gcc/config/aarch64/iterators.md | 15 --
5 files changed, 56 insertions(+), 277 deletions(-)

Upstream: gcc.gnu.org


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