[ARM] Add support for -mpure-code in thumb-1 (v6m)

Programming / Compilers / GCC - clyon [138bc75d-0d04-0410-961f-82ee72b054a4] - 17 December 2019 15:43 EST

This patch extends support for -mpure-code to all thumb-1 processors, by removing the need for MOVT.

Symbol addresses are built using upper8_15, upper0_7, lower8_15 and lower0_7 relocations, and constants are built using sequences of movs/adds and lsls instructions.

The extension of the *thumb1_movhf pattern uses always the same size (6) although it can emit a shorter sequence when possible. This is similar to what *arm32_movhf already does.

CASE_VECTOR_PC_RELATIVE is now false with -mpure-code, to avoid generating invalid assembly code with differences from symbols from two different sections (the difference cannot be computed by the assembler).

Tests pr45701-[12].c needed a small adjustment to avoid matching upper8_15 when looking for the r8 register.

Test no-literal-pool.c is augmented with __fp16, so it now uses

Test thumb1-Os-mult.c generates an inline code sequence with-mpure-code and computes the multiplication by using a sequence of add/shift rather than using the multiply instruction, so we skip it in presence of -mpure-code.

With -mcpu=cortex-m0, the pure-code/no-literal-pool.c fails because code like: static char *p = "Hello World"; char * testchar () { return p + 4; }

generates 2 indirections (I removed non-essential directives/code) .section .rodata .LC0: .ascii "Hello World\000" .data p: .word .LC0 .section .rodata .LC2: .word p .section .text,"0x20000006",%progbits testchar: push {r7, lr} add r7, sp, #0 movs r3, #:upper8_15:#.LC2 lsls r3, #8 adds r3, #:upper0_7:#.LC2 lsls r3, #8 adds r3, #:lower8_15:#.LC2 lsls r3, #8 adds r3, #:lower0_7:#.LC2 ldr r3, [r3] ldr r3, [r3] adds r3, r3, #4 movs r0, r3 mov sp, r7 @ sp needed pop {r7, pc}

By contrast, when using -mcpu=cortex-m4, the code looks like: .section .rodata .LC0: .ascii "Hello World\000" .data p: .word .LC0 testchar: push {r7} add r7, sp, #0 movw r3, #:lower16:p movt r3, #:upper16:p ldr r3, [r3] adds r3, r3, #4 mov r0, r3 mov sp, r7 pop {r7} bx lr

I haven't found yet how to make code for cortex-m0 apply upper/lower relocations to "p" instead of .LC2. The current code looks functional, but could be improved.

2019-10-18 Christophe Lyon

- config/arm/arm-protos.h (thumb1_gen_const_int): Add new prototype.
- config/arm/arm.c (arm_option_check_internal): Remove restriction on MOVT for -mpure-code. (thumb1_gen_const_int): New function. (thumb1_legitimate_address_p): Support -mpure-code. (thumb1_rtx_costs): Likewise. (thumb1_size_rtx_costs): Likewise. (arm_thumb1_mi_thunk): Likewise.
- config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Likewise.
- config/arm/thumb1.md (thumb1_movsi_symbol_ref): New. (*thumb1_movhf): Support -mpure-code.

- gcc.target/arm/pr45701-1.c: Adjust for -mpure-code.
- gcc.target/arm/pr45701-2.c: Likewise.
- gcc.target/arm/pure-code/no-literal-pool.c: Add tests for __fp16.
- gcc.target/arm/pure-code/pure-code.exp: Remove thumb2 and movt conditions.
- gcc.target/arm/thumb1-Os-mult.c: Skip if -mpure-code is used.

2e94764fe22 [ARM] Add support for -mpure-code in thumb-1 (v6m)
gcc/ChangeLog | 15 ++++
gcc/config/arm/arm-protos.h | 1 +
gcc/config/arm/arm.c | 88 +++++++++++++++++++---
gcc/config/arm/arm.h | 8 +-
gcc/config/arm/thumb1.md | 69 +++++++++++++++--
gcc/doc/invoke.texi | 3 +-
gcc/testsuite/ChangeLog | 10 +++
gcc/testsuite/gcc.target/arm/pr45701-1.c | 2 +-
gcc/testsuite/gcc.target/arm/pr45701-2.c | 2 +-
.../gcc.target/arm/pure-code/no-literal-pool.c | 14 +++-
.../gcc.target/arm/pure-code/pure-code.exp | 9 +--
gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c | 1 +
12 files changed, 192 insertions(+), 30 deletions(-)

Upstream: gcc.gnu.org

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