[PR83370][AARCH64]Use tighter register constraint for sibcall patterns

Programming / Compilers / GCC - renlin [138bc75d-0d04-0410-961f-82ee72b054a4] - 1 February 2018 13:02 EST

In aarch64 backend, ip0/ip1 register will be used in the prologue/epilogue as temporary register.

When the compiler is performing sibcall optimization. It has the chance to use ip0/ip1 register for indirect function call to hold the address. However, those two register might be clobbered by the epilogue code which makes the last sibcall instruction invalid.

The patch here renames the register class CALLER_SAVE_REGS to TAILCALL_ADDR_REGS to reflect its usage, and remove IP registers from this class.


2018-02-01 Renlin Li

PR target/83370
- config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle TAILCALL_ADDR_REGS. (aarch64_register_move_cost): Likewise.
- config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to TAILCALL_ADDR_REGS. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to TAILCALL_ADDR_REGS. Remove IP registers.
- config/aarch64/aarch64.md (Ucs): Update register constraint.


2018-02-01 Richard Sandiford

PR target/83370
- gcc.target/aarch64/pr83370.c: New.

007246f7572 [PR83370][AARCH64]Use tighter register constraint for sibcall patterns.
gcc/ChangeLog | 13 +++++++++++++
gcc/config/aarch64/aarch64.c | 6 +++---
gcc/config/aarch64/aarch64.h | 6 +++---
gcc/config/aarch64/constraints.md | 4 ++--
gcc/testsuite/ChangeLog | 5 +++++
gcc/testsuite/gcc.target/aarch64/pr83370.c | 22 ++++++++++++++++++++++
6 files changed, 48 insertions(+), 8 deletions(-)

Upstream: gcc.gnu.org

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