IBM Z: Add pattern for load truth value of comparison into reg

Programming / Compilers / GCC - krebbel [138bc75d-0d04-0410-961f-82ee72b054a4] - 7 November 2019 11:52 EST

The RTXs used to express an overflow condition check in add/sub/mul are too complex for if conversion. However, there is code in noce_emit_store_flag which generates a simple CC compare as the base for using a conditional load. All we have to do is to provide a pattern to store the truth value of a CC compare into a GPR.

Done with the attached patch.

2019-11-07 Andreas Krebbel

- config/s390/s390.md ("*cstorecc_z13"): New insn_and_split pattern.

gcc/testsuite/ChangeLog:

2019-11-07 Andreas Krebbel

- gcc.target/s390/addsub-signed-overflow-1.c: Expect lochi instructions to be used.
- gcc.target/s390/addsub-signed-overflow-2.c: Likewise.
- gcc.target/s390/mul-signed-overflow-1.c: Likewise.
- gcc.target/s390/mul-signed-overflow-2.c: Likewise.
- gcc.target/s390/vector/vec-scalar-cmp-1.c: Check for 32 and 64 bit variant of lochi. Swap the values for the lochi's.
- gcc.target/s390/zvector/vec-cmp-1.c: Likewise.

1cef83424c0 IBM Z: Add pattern for load truth value of comparison into reg
gcc/ChangeLog | 5 ++
gcc/config/s390/s390.md | 15 +++++
gcc/testsuite/ChangeLog | 11 ++++
.../gcc.target/s390/addsub-signed-overflow-1.c | 2 +
.../gcc.target/s390/addsub-signed-overflow-2.c | 2 +
.../gcc.target/s390/mul-signed-overflow-1.c | 2 +
.../gcc.target/s390/mul-signed-overflow-2.c | 2 +
.../gcc.target/s390/vector/vec-scalar-cmp-1.c | 18 ++++--
gcc/testsuite/gcc.target/s390/zvector/vec-cmp-1.c | 72 ++++++++++++++--------
9 files changed, 99 insertions(+), 30 deletions(-)

Upstream: gcc.gnu.org


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