anv: implement gen12 post sync pipe control workaround

Graphics / Mesa 3D Graphics Library / Mesa - Lionel Landwerlin [intel.com] - 5 February 2020 00:25 UTC

Same as Skylake.

v2: Restrict to A0

bcb611361b0 anv: implement gen12 post sync pipe control workaround
src/intel/vulkan/genX_cmd_buffer.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

Upstream: cgit.freedesktop.org


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