i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin

Graphics / Mesa 3D Graphics Library / Mesa - Kenneth Graunke [whitecape.org] - 22 May 2018 17:02 EDT

We'd like to start using soft-pin to assign BO addresses up front, and never move them again. Our previous plan for dealing with 48-bit VF cache bugs was to relocate vertex buffers to the low 4GB, so we'd never have addresses that alias in the low 32 bits. But that requires moving buffers dynamically.

This patch tracks the last seen BO address for each vertex/index buffer, and emits a VF cache invalidate if the high bits change. (Ideally, we won't hit this case very often.) This should work for the soft-pin case, but unfortunately won't work in the relocation case, as we don't actually know the addresses. So, we have to use both methods.

v2: Mention that the cache uses a tuple more explicitly (suggested by Scott). Mention "single batch" too (suggested by Chris).

92f01fc5f9 i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.
src/mesa/drivers/dri/i965/brw_context.h | 6 +++
src/mesa/drivers/dri/i965/genX_state_upload.c | 63 +++++++++++++++++++++++++++
2 files changed, 69 insertions(+)

Upstream: cgit.freedesktop.org


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