i965: Reimplement all the PIPE_CONTROL rules

Graphics / Mesa 3D Graphics Library / Mesa - Kenneth Graunke [whitecape.org] - 12 March 2019 02:32 EDT

This implements virtually all documented PIPE_CONTROL restrictions in a centralized helper. You now simply ask for the operations you want, and the pipe control "brain" will figure out exactly what pipe controls to emit to make that happen without tanking your system.

The hope is that this will fix some intermittent flushing issues as well as GPU hangs. However, it also has a high risk of causing GPU hangs and other regressions, as this is a particularly sensitive area and poking the bear isn't always advisable.

Mark Janes noted that this patch helps with some GPU hangs on Icelake.

This does re-enable the VF Invalidate => Write Immediate workaround on Gen8, which had been disabled (bug 103787) due to GPU hangs. The old code did this workaround after another which would have added CS stall bits, so it missed a workaround. The new code orders them properly and appears to work.

v4: Don't pass "bo, offset, imm" to a recursive CS stall (caught by Topi Pohjolainen), drop Gen10 workarounds that are unnecessary for production hardware.

1467deb5432 i965: Reimplement all the PIPE_CONTROL rules.
src/mesa/drivers/dri/i965/genX_pipe_control.c | 539 +++++++++++++++++++-------
1 file changed, 403 insertions(+), 136 deletions(-)

Upstream: cgit.freedesktop.org


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