i965: Rework Sandy Bridge HiZ and stencil layouts

Graphics / Mesa 3D Graphics Library / Mesa - Jason Ekstrand [intel.com] - 1 June 2017 18:33 EDT

Sandy Bridge does not technically support mipmapped depth/stencil. In order to work around this, we allocate what are effectively completely separate images for each miplevel, ensure that they are page-aligned, and manually offset to them. Prior to layered rendering, this was a simple matter of setting a large enough halign/valign.

With the advent of layered rendering, however, things got more complicated. Now, things weren't as simple as just handing a surface off to the hardware. Any miplevel of a normally mipmapped surface can be considered as just an array surface given the right qpitch. However, the hardware gives us no capability to specify qpitch so this won't work. Instead, the chosen solution was to use a new "all slices at each LOD" layout which laid things out as a mipmap of arrays rather than an array of mipmaps. This way you can easily offset to any of the miplevels and each is a valid array.

Unfortunately, the "all slices at each lod" concept missed one fundamental thing about SNB HiZ and stencil hardware: It doesn't just always act as if you're always working with a non-mipmapped surface, it acts as if you're always working on a non-mipmapped surface of the same size as LOD0. In other words, even though it may only write the upper-left corner of each array slice, the qpitch for the array is for a surface the size of LOD0 of the depth surface. This mistake causes us to under-allocate HiZ and stencil in some cases and also to accidentally allow different miplevels to overlap. Sadly, piglit test coverage didn't quite catch this until I started making changes to the resolve code that caused additional HiZ resolves in certain tests.

This commit switches Sandy Bridge HiZ and stencil over to a new scheme that lays out the non-zero miplevels horizontally below LOD0. This way they can all have the same qpitch without interfering with each other. Technically, the miplevels still overlap, but things are spaced out enough that each page is only in the "written area" of one LOD.

Cc: "17.0 17.1"

10903d2 i965: Rework Sandy Bridge HiZ and stencil layouts
src/mesa/drivers/dri/i965/brw_blorp.c | 11 ++-
src/mesa/drivers/dri/i965/brw_tex_layout.c | 100 ++++++++++++++++++++++----
src/mesa/drivers/dri/i965/gen6_depth_state.c | 4 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 11 +--
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 37 +++++++++-
5 files changed, 134 insertions(+), 29 deletions(-)

Upstream: cgit.freedesktop.org

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