i965/gen9: Use custom MOCS entries set up by the kernel

Graphics / Mesa 3D Graphics Library / Mesa - Francisco Jerez [riseup.net] - 16 July 2015 05:48 UTC

Instead of relying on hardware defaults the i915 kernel driver is going program custom MOCS tables system-wide on Gen9 hardware. The "WT" entry previously used for renderbuffers had a number of problems: It disabled caching on eLLC, it used a reserved L3 cacheability setting, and it used to override the PTE controls making renderbuffers always WT on LLC regardless of the kernel's setting. Instead use an entry from the new MOCS tables with parameters: TC=LLC/eLLC, LeCC=PTE, L3CC=WB.

The "WB" entry previously used for anything other than renderbuffers has moved to a different index in the new MOCS tables but it should have the same caching semantics as the old entry.

Even though the corresponding kernel change ("drm/i915: Added Programming of the MOCS") is in a way an ABI break it doesn't seem necessary to check that the kernel is recent enough because the change should only affect Gen9 which is still unreleased hardware.

v2: Update MOCS values for the new Android-incompatible tables introduced in v7 of the kernel patch.

Cc: 10.6 Reference: http://lists.freedesktop.org/archives/intel-gfx/2015-July/071080.html

af76892 i965/gen9: Use custom MOCS entries set up by the kernel.
src/mesa/drivers/dri/i965/brw_defines.h | 11 ++++++-----
src/mesa/drivers/dri/i965/gen8_surface_state.c | 3 +--
2 files changed, 7 insertions(+), 7 deletions(-)

Upstream: cgit.freedesktop.org

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