iris: implement gen12 post sync pipe control workaround

Graphics / Mesa 3D Graphics Library / Mesa - Lionel Landwerlin [intel.com] - 5 February 2020 00:25 UTC

Like Skylake, Gen12 requires a workaround for PIPE_CONTROLs using a post-sync operation.

v2: Restrict to A0

19e7bcee174 iris: implement gen12 post sync pipe control workaround
src/gallium/drivers/iris/iris_state.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)

Upstream: cgit.freedesktop.org


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