SPI_SHADER_COL_FORMAT allocates export memory and CB_SHADER_MASK map them to higher MRTs if necessary. The hardware allows to remap MRTs to avoid holes somehow.
For example, if we have a scenario where MRT0 is unused and only MRT1 and MRT2 are used, SPI_SHADER_COL_FORMAT is 0x77 and CB_SHADER_MASK/CB_TARGET_MASK are 0x770 (this assumes SPI_SHADER_UINT16_ABGR is set).
This allows us to remove one workaround that was added for fixing GPU hangs with DXVK. I think this is because SPI_SHADER_COL_FORMAT expects contiguous MRTs to be allocated.
7a5e6fd25f2 radv: add support for MRTs compaction to avoid holes
src/amd/compiler/aco_instruction_selection.cpp | 18 ++++++---
src/amd/vulkan/radv_nir_to_llvm.c | 3 +-
src/amd/vulkan/radv_pipeline.c | 51 ++++++++++++++------------
src/amd/vulkan/radv_shader_info.c | 12 ------
4 files changed, 41 insertions(+), 43 deletions(-)