Debugging a shader-db reported cycle count regression from the tex coalescing, I eventually figured out that the texture latencies were totally bogus. Really fixing it will probably involve mirroring
vc4_qir_schedule.c's texture fifo management here.
d40a321 vc4: Add a note for the future about texture latency calculation.
src/gallium/drivers/vc4/vc4_qpu_schedule.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
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