coreboot_tables: Add PCIe info to coreboot table

Hardware / Coreboot - Jianjun Wang [mediatek.com] - 19 May 2022 16:34 UTC

Add 'lb_fill_pcie' function to pass PCIe information from coreboot to libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the __weak function.

ARM platform usually does not have common address for PCIe to access the configuration space of devices. Therefore, new API is added to pass the base address of PCIe controller for payloads to access PCIe devices.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024 BRANCH=cherry

d16c2aa6de coreboot_tables: Add PCIe info to coreboot table
payloads/libpayload/include/coreboot_tables.h | 7 +++++++
payloads/libpayload/include/sysinfo.h | 1 +
payloads/libpayload/libc/coreboot.c | 10 ++++++++++
src/commonlib/bsd/include/commonlib/bsd/cb_err.h | 7 ++++---
src/commonlib/include/commonlib/coreboot_tables.h | 9 +++++++++
src/include/boot/coreboot_tables.h | 2 ++
src/lib/coreboot_table.c | 18 ++++++++++++++++++
7 files changed, 51 insertions(+), 3 deletions(-)

Upstream: review.coreboot.org


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