This patch was initially based on the __memmove_power7 with some ideas from strncpy implementation for Power 9.
Improvements from __memmove_power7:
1. Use lxvl/stxvl for alignment code.
The code for Power 7 uses branches when the input is not naturally aligned to the width of a vector. The new implementation uses lxvl/stxvl instead which reduces pressure on GPRs. It also allows the removal of branch instructions, implicitly removing branch stalls and mispredictions.
2. Use of lxv/stxv and lxvl/stxvl pair is safe to use on Cache Inhibited memory.
On Power 10 vector load and stores are safe to use on CI memory for addresses unaligned to 16B. This code takes advantage of this to do unaligned loads.
The unaligned loads don't have a significant performance impact by themselves. However doing so decreases register pressure on GPRs and interdependence stalls on load/store pairs. This also improved readability as there are now less code paths for different alignments. Finally this reduces the overall code size.
3. Improved performance.
This version runs on average about 30% better than memmove_power7 for lengths larger than 8KB. For input lengths shorter than 8KB the improvement is smaller, it has on average about 17% better performance.
This version has a degradation of about 50% for input lengths in the 0 to 31 bytes range when dest is unaligned.
dd59655e93 powerpc64le: Optimized memmove for POWER10
sysdeps/powerpc/powerpc64/le/power10/memmove.S | 320 +++++++++++++++++++++
sysdeps/powerpc/powerpc64/multiarch/Makefile | 3 +-
sysdeps/powerpc/powerpc64/multiarch/bcopy.c | 9 +
.../powerpc/powerpc64/multiarch/ifunc-impl-list.c | 14 +
.../powerpc/powerpc64/multiarch/memmove-power10.S | 27 ++
.../powerpc/powerpc64/multiarch/memmove-power7.S | 4 +-
sysdeps/powerpc/powerpc64/multiarch/memmove.c | 16 +-
sysdeps/powerpc/powerpc64/power7/memmove.S | 2 +
8 files changed, 388 insertions(+), 7 deletions(-)