1. change control flow for L(more_2x_vec) to fall through to loop and jump for L(less_4x_vec) and L(less_8x_vec). This uses less code size and saves jumps for length > 4x VEC_SIZE.
2. For EVEX/AVX512 move L(less_vec) closer to entry.
3. Avoid complex address mode for length > 2x VEC_SIZE
4. Slightly better aligning code for the loop from the perspective of code size and uops.
5. Align targets so they make full use of their fetch block and if possible cache line.
6. Try and reduce total number of icache lines that will need to be pulled in for a given length.
7. Include "local" version of stosb target. For AVX2/EVEX/AVX512 jumping to the stosb target in the sse2 code section will almost certainly be to a new page. The new version does increase code size marginally by duplicating the target but should get better iTLB behavior as a result.
test-memset, test-wmemset, and test-bzero are all passing.
e59ced2384 x86: Optimize memset-vec-unaligned-erms.S
sysdeps/x86_64/memset.S | 10 +-
.../x86_64/multiarch/memset-avx2-unaligned-erms.S | 10 +-
.../multiarch/memset-avx512-unaligned-erms.S | 11 +-
.../x86_64/multiarch/memset-evex-unaligned-erms.S | 11 +-
.../x86_64/multiarch/memset-vec-unaligned-erms.S | 285 +++++++++++++++------
5 files changed, 232 insertions(+), 95 deletions(-)