baytrail: Enable PCIe common clock and ASPM

Hardware / Coreboot - Duncan Laurie [chromium.org] - 14 May 2014 22:07 UTC

Enable the config options to have the device enumeration layer configure common clock and ASPM for endpoints.

BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on rambi, check PCIe for ASPM and common clock:

lspci -vv -s 0:1c.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+

lspci -vv -s 1:00.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+

Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f

c6313db baytrail: Enable PCIe common clock and ASPM
src/soc/intel/baytrail/Kconfig | 2 ++
1 file changed, 2 insertions(+)

Upstream: review.coreboot.org

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