This adds support for detecting Zve32x, Zve32f, Zve64x and Zve64d on a system that does not support (or declare) the full V feature set.
Add fast path optimization for frexpl (128-bit IEEE quad precision) using a single unsigned comparison to identify normal floating-point numbers and return immediately via arithmetic on the exponent field. The implementation uses arithmetic operations hx = hx - (ex << 48) to adjust the exponent in place, which is simpler and more efficient than bit masking.
Add fast path optimization for frexpf using a single unsigned comparison to identify normal floating-point numbers and return immediately via arithmetic on the bit representation. The implementation uses asuint()/asfloat() from math_config.h and arithmetic operations to adjust the exponent, which generates better code than bit masking on ARM and RISC-V architectures.
Add fast path optimization for frexp using a single unsigned comparison to identify normal floating-point numbers and return immediately via arithmetic on the bit representation. The implementation uses asuint64()/asdouble() from math_config.h and arithmetic operations to adjust the exponent, which generates better code than bit masking on ARM and RISC-V architectures.
clang might generate an abort call when cleanup functions (set by __attribute__ ((cleanup)) calls functions not marked as nothrow.
bfb28b5ce89f3e950214b67ea95b45e3355c2caf removed the MMX idct_put and idct_add functions, because they were overridden by SSE2 versions (which use SSE2 only for the put/add part, not the actual IDCT).
This adds testing for the fix added in commit: 0fceed254559836b57ee05188deac649bc505d05 "nss: Group merge does not react to ERANGE during merge (bug 33361)" The in-use group size is increased large enough to trigger ERANGE for initial buffers and cause a retry.