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- First-draft release notes for 9.4.1 et al
- [autofit] Add support for Thai script
- vendorcode/amd/agesa/f14: update microcode
- Gummiboot: version 48
- Gummiboot: version 46
- Delete useless “-old” copies of icons
- Elementary: NEWS: Clean up news file before release
- chroma: remove dead CYUV support
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- Committing VTV Cygwin patch for Patrick Wollgast
- demux: ts: add PAT/PMT hotfix (fix #10650)
- amd/amdfam10: Add runtime ACPI _PSS generation
- Add preliminary Net Kit intro by Philippe Houdoin
- man: systemd.service(5): add some simple examples
- AMD Bald Eagle: Add binary PI vendorcode files
- Add DXVA2 HEVC HWAccel
- Add a side data type for audio service type
- Add DXVA2 HEVC HWAccel
- Add 32x32 DCT block transform
- css: Add a -gtk-icon-theme CSS property
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Beignet
Beignet is an open-source OpenCL implementation for Intel graphics cores on Linux.
Recent Activity
- add edge case detection for powr in utests
Meng Mengmeng: power(x,y) return Nan for x<0 in spec, so add that for powr.
Activity Earlier In The Year
- Add the disasm support for Gen8
Junyan He - GBE: add basic PHINode support in legalize pass
Zhigang Gong: Lack of the incomplete PHINode support currently. - GBE: add legalize pass to handle wide integers
Ruiling Song: This legalize pass will break wider integers like i128/i256/... - BDW: Add BDW Device id to gen binary generater and binary serialize in backend
Yang Rong - BDW: enable SLM in BDW.
Yang Rong: BDW's SLM control register change to L3CNTLREG, offset is 0x7034. - BDW: add some BDW function
Yang Rong: Add intel_gpgpu_load_vfe_state_gen8, intel_gpgpu_walker_gen8, intel_gpgpu_build_idrt_gen8. - BDW: Add gen8 surface state struct
Junyan He - BDW: Add class Gen8Context
Yang Rong: Now Gen8Context is almost same as Gen75Context, but still derive Gen8Context from GenContext for clearly. - BDW: Add Gen8Encoder and Gen7Encoder
Yang Rong: Class Gen8Encoder and Gen7Encoder derive from GenEncoder, and Gen75Encoder derive from Gen7Encode. - BDW: Add BDW instruction define
Yang Rong: Seperate GEN7 instruction and GEN8 instrunction.
Most Popular This Year
- Bump to version 0.8.0.
Zhigang Gong: This version brings many improvments compare to the last released version 0.3, so that we decide to bump the version to 0.8.0 directly. - Add clang/LLVM 3.5svn support
Zhigang Gong: The clang/llvm 3.3 has some minor bugs such as the vector ++/-- which was fixed in 3.4. - GBE: Support 64Bit register spill
Ruiling Song: Now we support DWORD & QWORD register spill/fill. v2: only add poolOffset by 1 when we meet QWord register and poolOffset is 1. v3: allocate reserved register pool unifiedly for src and dst register. - GBE: support getelementptr with ConstantExpr operand
Guo Yejun: Add support during LLVM IR -> Gen IR period when the first operand of getelementptr is ConstantExpr. - GBE: Optimize write_image instruction for simd8 mode
Zhigang Gong: On simd8 mode, we can put the u,v,w,x,r,g,b,a to a selection vector directly and don't need to assign those values again. - GBE: optimize sample instruction
Zhigang Gong: The U,V,W registers could be allocated to a selection vector directly. - GBE: add param to switch the behavior of math func
Guo Yejun: Add OCL_STRICT_CONFORMANCE to switch the behavior of math func, The funcs will be high precision with perf drops if it is 1, Fast path with good enough precision will be selected if it is 0. - BDW: Add class Gen8Context
Yang Rong: Now Gen8Context is almost same as Gen75Context, but still derive Gen8Context from GenContext for clearly. - BDW: Add BDW instruction define
Yang Rong: Seperate GEN7 instruction and GEN8 instrunction. - BDW: Add Gen8Encoder and Gen7Encoder
Yang Rong: Class Gen8Encoder and Gen7Encoder derive from GenEncoder, and Gen75Encoder derive from Gen7Encode.