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- GCC: libgo: update to Go 1.12.1
- android: nouveau: add support for nir
- Linux Kernel: Linux 5.1-rc1
- Partial implementation of SQL/JSON path language
- WINE: Release 4.4.
- modesetting: add tile property support
- add drop target support to welded widget
- Enable parallel query with SERIALIZABLE isolation
- Latest News (cont.)
- KJ: Add more SVG icons (Writer)
- x32: Add addr32 prefix to VSIB address
- core: merge branch 'th/routing-rule-pt1'
- networkd: Add bridge port capabilities
- nir: add partial loop unrolling support
- tableam: Add and use scan APIs
- msidb: Add support for importing database tables
- Update from POT, no content change
- Karasa Jaga: Add initial SVG icons
- Support for INCLUDE attributes in GiST indexes
- RISC-V: Add libstdc++ check-abi support
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Coreboot
Coreboot, formerly known as LinuxBIOS, provides a modern BIOS/firmware implementation for many modern processors and chipsets.
Activity Earlier In The Year
- soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature
Subrata Banik: This patch moves required Kconfig selection for enabling ASPM feature (like clk_pm, L1 state etc) from soc code to intel common pch base code. - mb/google/kahlee/variants/delan: Enable Weida touchscreen device
Ivy Jian: This change adds ACPI properties for WDT8752A device. - northbridge/intel/fsp_*: Remove legacy SoCs
zaolin: - Remove FSP Sandy/Ivybrige which are unused. - util/bucts: Add tool to manipulate BUC.TS bit on Intel targets
Arthur Heymans: The purpose of this tool is to manipulate and get information about the `Back Up Control, Top Swap` mechanism present on most Intel Southbridges. This tool is initially written by Peter Stuge. This tool makes it possible to have a backup mechanism for the bootblock by using the southbridges Back Up Control Top Swap. Sometimes it is also possible to circumvent vendor write protection mechanisms in order to flash coreboot. - src: Add required space after "switch"
Elyes HAOUAS - mb/asus/p5qc: Add p5ql_pro mainboard as variant
Angel Pons: Working:- SATA on southbridge ports- SATA on Marvell IDE controller ports- USB- COM1- PS/2 keyboard- DDR2 DIMMs- PCIe x16 PEG port- PCIe x1 ports- PCI ports- NIC (MAC address needs to be set in Kconfig or in a CBFS file)- S3 resume- Green audio line out connector (the rest is untested) Not working: - Floppy port. - siemens/mc_apl5: Add new mainboard variant mc_apl5
Mario Scheithauer: This mainboard is based on mc_apl1. - soc/intel/icelake: Make static IRQ mapping for PIC mode
Subrata Banik: This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC. - soc/intel/icelake: Make static IRQ mapping for ICP PCH pci devices
Subrata Banik: Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call due to PCH requirement change from CNP PCH onwards, hence making static IRQ mapping for pci_irqs.asl and pcie.asl - soc/intel/cannonlake: Add options for pcie ltr
Lijian Zhao: FSP can support enable/disable Pci express LTR (Latency Tolerance Reporting) mechanism through upd interface.
Coreboot Release Tags
- util/docker: Rename _CONTAINER_VERSION => _IMAGE_TAG
Nico Huber: This is so confusing, let's name it what it is ;) - nb/intel/sandybridge: Bump MRC_CACHE_VERSION
Patrick Rudolph: Commit 74203de "intel/sandybridge: Don't hardcode platform type" changed the MRC layout. Bump the version to prevent a boot error, if the cache isn't cleared on flashing a new coreboot version. Change-Id: Icd6f31bf0b30a42c66e18ab83d2434f9c3084211 - ifdtool: Add a list of known platforms that support IFD_VERSION_2
Furquan Shaikh: ifdtool has relied on one of the fields within FCBA(read_freq) to determine whether a platform supports IFD_VERSION_1 or IFD_VERSION_2. - vendorcode/intel: Add Kconfig option to get UDK_VERSION
Subrata Banik: This patch ensures if required SoC/FSP driver code can retrieve UDK version for a platform. - soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
Furquan Shaikh: BUG=b:70628116 - soc/intel/common/block/gspi: Add SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
Furquan Shaikh: Even though kaby lake and cannon lake are using the same GSPI controller, bit meanings (for polarity and state) in SPI_CS_CONTROL register are significantly different. - SeaBIOS: remove VERSION variable in coreboot Makefile
Alexander Couzens: SeaBIOS dropped support of VERSION variable and is reproducible without it. - buildgcc: use ${GDB_DIR} instead of gdb-${GDB_VERSION}
Stefan Reinauer: Bring gdb in sync with all other build targets. - lenovo/*: Remove unused MAINBOARD_VERSION
Vladimir Serbinenko: Change-Id: I88e889efe43b32e7efc59ea40d13e79209a27264
Most Popular This Year
- mainboard: Add ASUS Maximus IV GENE-Z
Tristan Corrick: Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.3 with kernel 4.9. - arm64: Add ARCH Timer
T Michael Turney: SoC sdm845 uses ARCH Timer - vboot: Add support for reading GBB flags
Furquan Shaikh: This change adds basic support for reading flags from GBB header located in "GBB" section on SPI flash. - mainboard: Add ASUS P8H61-M LX
Tristan Corrick: Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. - payloads: Add LinuxBoot payload in u-root mode
Philipp Deppenwiese: - Add LinuxBoot support - inteltool: Add some Skylake desktop ids
Nico Huber - libpayload-x86: Add common i8042 driver
Patrick Rudolph: Add a common i8042 driver that uses multiple overflowing fifos to seperate PS/2 port and PS/2 aux port. - msrtool: add VIA C7
Lubomir Rintel - acpi: Add support for generating ACPI _UPC
Duncan Laurie: This commit adds support for writing ACPI _UPC structures that help describe USB ports for the OS. This is a simple structure format which indicates what type of port it is and whether it is connectable. - cbfstool: Add region offset information to layout command
Werner Zeh: The layout command prints all FMAP regions in the final image among with the region size.