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Coreboot

Coreboot, formerly known as LinuxBIOS, provides a modern BIOS/firmware implementation for many modern processors and chipsets.

www.coreboot.org

Today's Activity

mb/google/brya/var/omnigul: Add memory config
Amanda Huang: Configure the rcomp, dqs and dq tables based on the schematic.

mb/google/geralt: Add USB3 HUB reset funtion to bootblock
Bo-Chen Chen: After powering on the device, we need to pull USB3_HUB_RST_L up to enable USB3 Hub.

crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7
Elyes Haouas

treewide: Remove duplicated include
Elyes Haouas: <device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>.

Yesterday's Activity

soc/intel/common/block: Add LPC BIOS decode lock
Tim Chu: The LPC BIOS decode lock bit is defined in EBG EDS documentation.

Other Activity This Week

mb/*: Remove lapic from devicetree
Arthur Heymans: The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase.

mb/intel/mtlrvp: Add romstage and configure LP5 memory parts
Ashish Kumar Mishra: This patch adds initial romstage code and spd data for LP5 memory parts for MTL-RVP.

vendorcode/intel/fsp/fsp2_0: add SPR-SP FSP header files
Jonathan Zhang: Intel Sapphire Rapids Scalable Processor was product launched on Jan.

drivers/intel/fsp2_0: Add saving MRC data after FSP-S option
Johnny Lin: When Kconfig SAVE_MRC_AFTER_FSPS is selected, save MRC training data after FSP-S instead of FSP-M.

mb/starlabs/starbook/adl: Make Type-C USB a standard port
Sean Rhodes: Change the Type-C USB 2.0 interface to a standard port, as the Type-C macro will not work in Linux (dmesg says the cable is faulty),

src/acpi: add debug message with concatenated string
Cliff Huang: add functions for concatenate OP add debug message containing concatenated string with string, value, or OPs

mb/siemens/mc_apl1/var/mc_apl5: Enable early POST
Jan Samek: Enable early POST code display on this variant using the common mc_apl1 baseboard functionality.

src/mb/prodrive/atlas: Add GPIOs for configuration
Maximilian Brune: CLKREQ Pins are intentionally not configured, because there seems to be a current Issue with FSP, that causes pci devices to not work if CLKREQ Pins are configured by coreboot.

nb/intel/gm45: Add remaining raminit code to support DDR2
Nico Huber: Add the remaining DDR2 code to program the registers for memory timings, ODT, RCOMP, and refresh mode; and perform receive-enable calibration.

nb/intel/gm45: Split DDR2 I/O init out
Nico Huber: Move DDR3 memory I/O init to its own function and add DDR2 memory I/O init.

nb/intel/gm45: Split DDR2 JEDEC init out
Nico Huber: Split JEDEC init into common and DDR3 specific parts and add the DDR2 specific init code.

nb/intel/gm45: Wedge DDR2 SPD support in
Nico Huber: Add initial support for DDR2.

Coreboot Release Tags

soc/intel/meteorlake: Select DISPLAY_FSP_VERSION_INFO_2
Saurabh Mishra: Changes include:- Add config for Meteor Lake SoC to select FirmwareVersionInfo.h using 'DISPLAY_FSP_VERSION_INFO_2'

ec/google/chromeec: Simplify error handling for GET_VERSION
Caveh Jalali: We don't need to check the lower level error code to determine if an EC call succeeded.

mb/google/skyrim: Select GOOGLE_SMBIOS_MAINBOARD_VERSION
Amanda Huang: Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:256723358 TEST=1.

drivers/i2c/tpm: Remove TI50_FIRMWARE_VERSION_NOT_SUPPORTED
Reka Norman: This workaround was added since reading the firmware version on Ti50 versions < 0.0.15 will cause the Ti50 to become unresponsive.

tpm: Correct TI50_FIRMWARE_VERSION_NOT_SUPPORTED help text
Yu-Ping Wu: Reading firmware_version register is supported on Ti50 version 0.22.4.

mg/google/corsola: Disable TI50_FIRMWARE_VERSION_NOT_SUPPORTED
Yu-Ping Wu: Reading Ti50 version is now supported on Ti50 version 0.22.4.

soc/intel/tigerlake: Disable DISPLAY_FSP_VERSION_INFO on IOT
Frans Hendriks: Build error for platforms using Intel FSP for TGL_IOT (FSP_TYPE_IOT).

mg/google/corsola: Enable TI50_FIRMWARE_VERSION_NOT_SUPPORTED
Yu-Ping Wu: Ti50 hasn't implemented version reading yet.

util/genbuild_h: micro-adjust the regexp used to set COREBOOT_MAJOR_VERSION
Idwer Vollering: On FreeBSD, every build target would show warnings from its builtin printf().

Revert "SeaBIOS: Update stable release to 1.15.0"
Paul Menzel: This reverts commit 2a8de6dafb7eec8ff9112b43888507fbc0d8f851. SeaBIOS 1.15.0 regresses on systems with NVMe devices [1]: > Greetings! Was this patch set tested on bare metal hardware? I'm > seeing "GRUB loading: Read Error" when attempting to boot from NVMe on > various Purism Librem devices (Intel Skylake thru Cometlake hardware).

Most Popular In The Past Month

Kconfig: Add option to compress ramstage with LZ4
Martin Roth: When ramstage is loaded asynchronously, as on the skyrim boards, the faster decompression of LZ4 allows for faster boot times than the tighter compression of LZMA.

payloads: Update GRUB2 stable version from 2.04 to 2.06
Paul Menzel: GRUB2 was released on June 8th, 2021 [1].

ifdtool: Determine max regions from IFD
Patrick Rudolph: IFDv1 always has 8 regions, while IFDv2 always has 16 regions. It's platform specific which regions are used or are reserved.

tree: Drop Intel Ice Lake support
Felix Singer: Intel Ice Lake is unmaintained and the only user of this platform ever was the Intel CRB (Customer Reference Board).

mainboard: Drop invalid `hyper_threading` option
Angel Pons: Drop the `hyper_threading` CMOS option from most boards, as it's most likely not working properly and causing problems.

Documentation: Add 4.20 release notes template and update index
Martin Roth: Also update Month abbreviations to full month names.

crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7
Elyes Haouas

vendorcode/intel/fsp/fsp2_0: add SPR-SP FSP header files
Jonathan Zhang: Intel Sapphire Rapids Scalable Processor was product launched on Jan.

util/inteltool: add support for EBG (Emmitsburg) PCH
Christian Walter: EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset. Its datasheet is Intel doc# 606161. Add Intel Emmitsburg PCH GPIO pin definitions. Also common code change is made to support Intel Emmitsburg PCH: a.

soc/intel/meteorlake: Enable support for common IRQ block
Kapil Porwal: Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows MTL boards to dynamically assign PCI IRQs.

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