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Coreboot

Coreboot, formerly known as LinuxBIOS, provides a modern BIOS/firmware implementation for many modern processors and chipsets.

www.coreboot.org

Activity Earlier In The Year

soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature
Subrata Banik: This patch moves required Kconfig selection for enabling ASPM feature (like clk_pm, L1 state etc) from soc code to intel common pch base code.

mb/google/kahlee/variants/delan: Enable Weida touchscreen device
Ivy Jian: This change adds ACPI properties for WDT8752A device.

northbridge/intel/fsp_*: Remove legacy SoCs
zaolin: - Remove FSP Sandy/Ivybrige which are unused.

util/bucts: Add tool to manipulate BUC.TS bit on Intel targets
Arthur Heymans: The purpose of this tool is to manipulate and get information about the `Back Up Control, Top Swap` mechanism present on most Intel Southbridges. This tool is initially written by Peter Stuge. This tool makes it possible to have a backup mechanism for the bootblock by using the southbridges Back Up Control Top Swap. Sometimes it is also possible to circumvent vendor write protection mechanisms in order to flash coreboot.

src: Add required space after "switch"
Elyes HAOUAS

mb/asus/p5qc: Add p5ql_pro mainboard as variant
Angel Pons: Working:- SATA on southbridge ports- SATA on Marvell IDE controller ports- USB- COM1- PS/2 keyboard- DDR2 DIMMs- PCIe x16 PEG port- PCIe x1 ports- PCI ports- NIC (MAC address needs to be set in Kconfig or in a CBFS file)- S3 resume- Green audio line out connector (the rest is untested) Not working: - Floppy port.

siemens/mc_apl5: Add new mainboard variant mc_apl5
Mario Scheithauer: This mainboard is based on mc_apl1.

soc/intel/icelake: Make static IRQ mapping for PIC mode
Subrata Banik: This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.

soc/intel/icelake: Make static IRQ mapping for ICP PCH pci devices
Subrata Banik: Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call due to PCH requirement change from CNP PCH onwards, hence making static IRQ mapping for pci_irqs.asl and pcie.asl

soc/intel/cannonlake: Add options for pcie ltr
Lijian Zhao: FSP can support enable/disable Pci express LTR (Latency Tolerance Reporting) mechanism through upd interface.

Coreboot Release Tags

util/docker: Rename _CONTAINER_VERSION => _IMAGE_TAG
Nico Huber: This is so confusing, let's name it what it is ;)

nb/intel/sandybridge: Bump MRC_CACHE_VERSION
Patrick Rudolph: Commit 74203de "intel/sandybridge: Don't hardcode platform type" changed the MRC layout. Bump the version to prevent a boot error, if the cache isn't cleared on flashing a new coreboot version. Change-Id: Icd6f31bf0b30a42c66e18ab83d2434f9c3084211

ifdtool: Add a list of known platforms that support IFD_VERSION_2
Furquan Shaikh: ifdtool has relied on one of the fields within FCBA(read_freq) to determine whether a platform supports IFD_VERSION_1 or IFD_VERSION_2.

vendorcode/intel: Add Kconfig option to get UDK_VERSION
Subrata Banik: This patch ensures if required SoC/FSP driver code can retrieve UDK version for a platform.

soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
Furquan Shaikh: BUG=b:70628116

soc/intel/common/block/gspi: Add SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
Furquan Shaikh: Even though kaby lake and cannon lake are using the same GSPI controller, bit meanings (for polarity and state) in SPI_CS_CONTROL register are significantly different.

SeaBIOS: remove VERSION variable in coreboot Makefile
Alexander Couzens: SeaBIOS dropped support of VERSION variable and is reproducible without it.

buildgcc: use ${GDB_DIR} instead of gdb-${GDB_VERSION}
Stefan Reinauer: Bring gdb in sync with all other build targets.

lenovo/*: Remove unused MAINBOARD_VERSION
Vladimir Serbinenko: Change-Id: I88e889efe43b32e7efc59ea40d13e79209a27264

Most Popular This Year

mainboard: Add ASRock H81M-HDS
Tristan Corrick: Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This board works quite well under coreboot.

selfboot: remove bounce buffers
Ronald G. Minnich: Bounce buffers used to be used in those cases where the payload might overlap coreboot. Bounce buffers are a problem for rampayloads as they need malloc. They are also an artifact of our x86 past before we had relocatable ramstage; only x86, out of the 5 architectures we support, needs them; currently they only seem to matter on the following chipsets: src/northbridge/amd/amdfam10/Kconfig src/northbridge/amd/lx/Kconfig src/northbridge/via/vx900/Kconfig src/soc/intel/fsp_baytrail/Kconfig src/soc/intel/fsp_broadwell_de/Kconfig The first three are obsolete or at least could be changed to avoid the need to have bounce buffers.

riscv: add support to block smp in each stage
Xiang Wang: Each stage performs some basic initialization (stack, HLS etc) and then call smp_pause to enter the single-threaded state.

riscv: add physical memory protection (PMP) support
Xiang Wang: These codes are written by me based on the privileged instruction set.

fsp_broadwell_de: Switch to common SPI controller driver
Werner Zeh: The common SPI controller driver in src/southbridge/intel/common does match the SPI controller included in the PCH of Broadwell-DE SoC.

cbfstool: add unprocessed flag for file exporting
Joel Kitching: Add an unprocessed flag (-U) which modifies how files are exported.

riscv: add support for supervisor binary interface (SBI)
Xiang Wang: SBI is runtime service for OS.

Add selfboot to the romstage
Ronald G. Minnich: Now that bounce buffers are gone, and we can elide the selfload checking code at build time, it is safe to .

toolchain: Add POSTCAR as a stage we have a toolchain for
Patrick Georgi: Fixes building vb2lib for postcar.

console: Enable CONSOLE_USB by default
Nico Huber: It seems to be the only user of the USB debug driver.

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