Coreboot
Coreboot, formerly known as LinuxBIOS, provides a modern BIOS/firmware implementation for many modern processors and chipsets.
www.coreboot.org
Other Activity This Week
- mb/*: Remove lapic from devicetree
Arthur Heymans: The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. - mb/intel/mtlrvp: Add romstage and configure LP5 memory parts
Ashish Kumar Mishra: This patch adds initial romstage code and spd data for LP5 memory parts for MTL-RVP. - vendorcode/intel/fsp/fsp2_0: add SPR-SP FSP header files
Jonathan Zhang: Intel Sapphire Rapids Scalable Processor was product launched on Jan. - drivers/intel/fsp2_0: Add saving MRC data after FSP-S option
Johnny Lin: When Kconfig SAVE_MRC_AFTER_FSPS is selected, save MRC training data after FSP-S instead of FSP-M. - mb/starlabs/starbook/adl: Make Type-C USB a standard port
Sean Rhodes: Change the Type-C USB 2.0 interface to a standard port, as the Type-C macro will not work in Linux (dmesg says the cable is faulty), - src/acpi: add debug message with concatenated string
Cliff Huang: add functions for concatenate OP add debug message containing concatenated string with string, value, or OPs - mb/siemens/mc_apl1/var/mc_apl5: Enable early POST
Jan Samek: Enable early POST code display on this variant using the common mc_apl1 baseboard functionality. - src/mb/prodrive/atlas: Add GPIOs for configuration
Maximilian Brune: CLKREQ Pins are intentionally not configured, because there seems to be a current Issue with FSP, that causes pci devices to not work if CLKREQ Pins are configured by coreboot. - nb/intel/gm45: Add remaining raminit code to support DDR2
Nico Huber: Add the remaining DDR2 code to program the registers for memory timings, ODT, RCOMP, and refresh mode; and perform receive-enable calibration. - nb/intel/gm45: Split DDR2 I/O init out
Nico Huber: Move DDR3 memory I/O init to its own function and add DDR2 memory I/O init. - nb/intel/gm45: Split DDR2 JEDEC init out
Nico Huber: Split JEDEC init into common and DDR3 specific parts and add the DDR2 specific init code. - nb/intel/gm45: Wedge DDR2 SPD support in
Nico Huber: Add initial support for DDR2.