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google/reef: Add pull up 20K for LPC SERIRQ

Hardware / Coreboot - Kane Chen [intel.com] - 2 August 2016 11:41 UTC

per hw team's check and info from EDS, this pin needs to be pu 20K. Otherwise SoC may not notice interrupt request from EC over LPC because SERIRQ line is floating.

BUG=chrome-os-partner:55586 BRANCH=none TEST=boot ok and Quanta factory verified the keyboard issue is gone

5976143 google/reef: Add pull up 20K for LPC SERIRQ
src/mainboard/google/reef/gpio.h | 2 +-
src/soc/intel/apollolake/lpc_lib.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)

Upstream: review.coreboot.org