intel/bayleybay: Add Intel's Bayley Bay mainboard

Hardware / Coreboot - Martin Roth [gmail.com] - 30 May 2014 10:34 UTC

Bay Trail-I Platform – Bayley Bay-I Customer Reference Board

The Bayley Bay CRB-I is a dual-channel DDR3L SO-DIMM non-ECC platform. It is designed to support the Bay Trail-I SoC.

This implementation uses the Intel FSP (Vist the Intel FSP website for details on FSP architecture and support). This code does not currently support S3. All other features and IO ports are functional. Booted on Ubuntu 14.04, Mint 16, Fedora 20 with SeaBIOS payload. Memtest86, FWTS, and other tests pass.

Notes:- Generates a 2MB binary to be flashed to the upper 2MB of the ROM, to preserve the existing Intel Flash Descriptor & TXE binary.- Tested with B0 & B3 Baytrail I parts

Board support page will be updated on acceptance.

Change-Id: I80c836c7590f2dc25ec854e7a0bb939024cea600

d75800c intel/bayleybay: Add Intel's Bayley Bay mainboard
src/mainboard/intel/Kconfig | 3 +
src/mainboard/intel/bayleybay_fsp/Kconfig | 111 +++++++++
src/mainboard/intel/bayleybay_fsp/Makefile.inc | 21 ++
.../intel/bayleybay_fsp/acpi/mainboard.asl | 25 ++
src/mainboard/intel/bayleybay_fsp/acpi_tables.c | 257 ++++++++++++++++++++
src/mainboard/intel/bayleybay_fsp/board_info.txt | 4 +
src/mainboard/intel/bayleybay_fsp/cmos.layout | 134 ++++++++++
src/mainboard/intel/bayleybay_fsp/devicetree.cb | 81 ++++++
src/mainboard/intel/bayleybay_fsp/dsdt.asl | 57 +++++
src/mainboard/intel/bayleybay_fsp/fadt.c | 35 +++
src/mainboard/intel/bayleybay_fsp/gpio.c | 224 +++++++++++++++++
src/mainboard/intel/bayleybay_fsp/irqroute.c | 22 ++
src/mainboard/intel/bayleybay_fsp/irqroute.h | 72 ++++++
src/mainboard/intel/bayleybay_fsp/mainboard.c | 48 ++++
src/mainboard/intel/bayleybay_fsp/romstage.c | 176 ++++++++++++++
src/mainboard/intel/bayleybay_fsp/thermal.h | 33 +++
16 files changed, 1303 insertions(+)

Upstream: review.coreboot.org

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