intel/fsp_baytrail: Add PCI Root Port IRQ Routing

Hardware / Coreboot - Martin Roth [gmail.com] - 12 March 2015 14:35 UTC

This change generates the ASL tables needed for the PCIe bridge routing.

It generates this ASL (swizzled for each of the 8 functions) Name(RP1P, Package() { Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, }) Name(RP1A, Package() { Package() {0x0000ffff, 0, 0, 20 }, Package() {0x0000ffff, 1, 0, 21 }, Package() {0x0000ffff, 2, 0, 22 }, Package() {0x0000ffff, 3, 0, 23 }, }) Device(RP01) { Name(_ADR, 0x1c0001) Name(_PRW, Package() { 0, 0 }) Method(_PRT,0) { If(PICM) { Return (RP1A) } Else { Return (RP1P) } } }

Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30

d08057a intel/fsp_baytrail: Add PCI Root Port IRQ Routing
src/mainboard/intel/bayleybay_fsp/irqroute.h | 38 ++++++++------
src/mainboard/intel/minnowmax/irqroute.h | 38 ++++++++------
src/soc/intel/fsp_baytrail/acpi/irq_helper.h | 69 +++++++++++++++++++++++++-
src/soc/intel/fsp_baytrail/acpi/irqroute.asl | 7 +++
src/soc/intel/fsp_baytrail/baytrail/irq.h | 3 ++
5 files changed, 123 insertions(+), 32 deletions(-)

Upstream: review.coreboot.org

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