intel/kunimitsu: Enable 20K PU on LPC_LAD 0-3

Hardware / Coreboot - pchandri [intel.com] - 15 January 2016 05:03 UTC

At S0, S0ix and S3 LPC LAD signals are are floated at 400~500mV.

BRANCH=chrome-os-partner:48331 BUG=None TEST=Build and Boot kunimitsu

Change-Id: I2e2654ac89f8e0c8d6ab1af31d0bd5a0d4c43db8

ff25b75 intel/kunimitsu: Enable 20K PU on LPC_LAD 0-3
src/mainboard/intel/kunimitsu/gpio.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

Upstream: review.coreboot.org

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