libpayload: usb: ehci: Honor 10ms reset recovery period

Hardware / Coreboot - Julius Werner [chromium.org] - 29 October 2014 13:20 UTC

This patch adds the 10ms TRSTRCY delay between a reset and the following Set Address command that is required by the USB 2.0 specification to the EHCI root hub driver. The generic_hub driver that's used for XHCI and external hubs already included this delay. This is such a glaring
violation of the spec that I'm really amazed how many USB 2.0 devices we tested before seemed perfectly fine with responding to a Set Address within 2 microframes of the reset...

It also increases the port reset hold delay by one millisecond to avoid an ugly race condition on Tegra SoCs: they decided to time the 50ms themselves instead of relying on the CPU to do it (fair enough), and to automatically transition Port Reset to 0 and Port Enable to 1 after that (bad idea). If the CPU's read-modify-write to clear Port Reset races exactly with the host controller setting Port Enable, we may end up clearing the bit again and going into the companion controller handoff path later on. The added millisecond shouldn't cause any problems for other host controllers and is not a big deal compared to other delays in this code path.

BUG=chrome-os-partner:26749 TEST=Run several dozen reboot loops with The USB Stick of Death (TM) (a blue Patriot XT 13fe:5200 with bcdDevice = 1.00), make sure it always gets detected correctly.

Original-Change-Id: Idd3329ae6d7e5e1c07a84a5475549b3459836b31

1c6d919 libpayload: usb: ehci: Honor 10ms reset recovery period
payloads/libpayload/drivers/usb/ehci_rh.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)

Upstream: review.coreboot.org

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