mips: add c0 register access plumbing

Hardware / Coreboot - Vadim Bendebury [chromium.org] - 7 April 2015 12:38 UTC

C0 is a coprocessor register set defined in certain MIPS architectures. This patch adds macros necessary to access the registers and a couple of helper macros to access two particular registers needed in the next patch.

The definitions come straight from arch/mips/include/asm/mipsregs.h in the 3.14 kernel tree.

BRANCH=none BUG=chrome-os-partner:31438 TEST=the following patch demonstrates timer counter C0 register configuration and use.

Change-Id: Ia5d52ffa75f2dd66d4cee3a4ed0af5122ccb2113

fc934b2 mips: add c0 register access plumbing
src/arch/mips/include/arch/cpu.h | 48 ++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)

Upstream: review.coreboot.org

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