nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage

Hardware / Coreboot - Timothy Pearson [raptorengineeringinc.com] - 31 March 2016 16:09 UTC

Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console.

Also clear the DRAM ECC sync flood bits during DRAM training and initial ramstage execution.

Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15

b3ddf83 nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
src/northbridge/amd/amdfam10/misc_control.c | 46 ++++++++++++++++++++++++
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 ++
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 +
src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 10 ------
4 files changed, 49 insertions(+), 10 deletions(-)

Upstream: review.coreboot.org

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