This adds the northbridge initialization pieces for Intel's Atom C2000 processor (Formerly Rangeley). It is intended to be used with the Intel Atom C2000 FSP and does not contain all of the pieces that would otherwise be required for initialization.
Not currently supported: S3 suspend/resume CAR memory Migration (No early cbmem console) SMM
Change-Id: I7665212c892d9a08ecf35d7be70d0afe5fd2c77b
2963ae7 northbridge/intel: Add fsp_rangeley northbridge support
src/northbridge/intel/Kconfig | 1 +
src/northbridge/intel/Makefile.inc | 1 +
src/northbridge/intel/fsp_rangeley/Kconfig | 92 ++++++
src/northbridge/intel/fsp_rangeley/Makefile.inc | 39 +++
src/northbridge/intel/fsp_rangeley/acpi.c | 66 +++++
.../intel/fsp_rangeley/acpi/hostbridge.asl | 138 +++++++++
.../intel/fsp_rangeley/acpi/rangeley.asl | 41 +++
src/northbridge/intel/fsp_rangeley/chip.h | 63 ++++
src/northbridge/intel/fsp_rangeley/fsp/Kconfig | 49 ++++
.../intel/fsp_rangeley/fsp/Makefile.inc | 21 ++
.../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 177 ++++++++++++
.../intel/fsp_rangeley/fsp/chipset_fsp_util.h | 52 ++++
src/northbridge/intel/fsp_rangeley/northbridge.c | 302 ++++++++++++++++++++
src/northbridge/intel/fsp_rangeley/northbridge.h | 78 +++++
src/northbridge/intel/fsp_rangeley/port_access.c | 72 +++++
src/northbridge/intel/fsp_rangeley/raminit.c | 44 +++
src/northbridge/intel/fsp_rangeley/udelay.c | 68 +++++
17 files changed, 1304 insertions(+)
Upstream: review.coreboot.org