Some GPIO pins are shared with (disabled) PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, we cannot mark 0:14.4 disabled in devicetree just yet.
Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d
7809356 pcengines/apu1: Implement board GPIOs
src/mainboard/pcengines/apu1/BiosCallOuts.c | 3 +-
src/mainboard/pcengines/apu1/Makefile.inc | 2 +
src/mainboard/pcengines/apu1/devicetree.cb | 1 +
src/mainboard/pcengines/apu1/gpio_ftns.c | 68 +++++++++++++++++++++++++++
src/mainboard/pcengines/apu1/gpio_ftns.h | 47 ++++++++++++++++++
src/mainboard/pcengines/apu1/mainboard.c | 19 ++++++++
src/mainboard/pcengines/apu1/romstage.c | 41 ++++++++++++++++
7 files changed, 180 insertions(+), 1 deletion(-)
Upstream: review.coreboot.org