Rambi has 3 pins that need to be configured for SCI and SMI:
1. GPIO_CORE[0] - runtime SCI pin 2. GPIO_SUS[7] - SMI for firmware lid events 3. GPIO_SUS[0] - wake pin for S3 wakes from EC.
Configure these pins now that the rest of the infrastructure is in place. The one thing that is yet to work is runtime SCI for lid events once booted.
BUG=chrome-os-partner:23505 BRANCH=None TEST=built and booted. lid close at rec screen works. And wake from S3 with a keyboard press works.
Change-Id: I5f8e38ec5f4cf1a8ef7aa7fcee9abc344d9b184f
59cd621 rambi: enable SCI and SMI gpios
src/mainboard/google/rambi/gpio.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
Upstream: review.coreboot.org