rk3399: add GPIO register definitions for SDMMC0

Hardware / Coreboot - Vadim Bendebury [chromium.org] - 18 May 2016 13:21 UTC

The code needs to be able to set drive strength for the pins used for SDMMC0 interface. This patch adds the definitions for the two registers, as per page 378 of the RK3399 TRM Part 1.

Instead of calculation of the reserved range size just use known offsets of the registers included in the structure.

BRANCH=none BUG=chrome-os-partner:53257 TEST=with the upcoming driver change it is possible to boot chrome OS on Gru from various micro SD cards which were failing before.

Change-Id: I63bf37432ec7f3bdf7e9c6a79d51c31de122dae9

a9cd4a2 rk3399: add GPIO register definitions for SDMMC0
src/soc/rockchip/rk3399/include/soc/grf.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)

Upstream: review.coreboot.org

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