rockchip: rk3399: add routines to set vop clocks

Hardware / Coreboot - Shunqian Zheng [rock-chips.com] - 18 May 2016 13:14 UTC

Let vop aclk sources from CPLL, and vop dclk from NPLL.

The dclk freq is decided by the edid mode pixel_clock which may require high accuracy like 252750KHz. The pll_para_config() can calculate the dividers for PLL to output desired clock.

BRANCH=none BUG=chrome-os-partner:51537 TEST=check display with the other patches

Change-Id: I12cf27d3d1177a8b1c4cfbd7c0be10204e3d3142

c7f32a5 rockchip: rk3399: add routines to set vop clocks
src/soc/rockchip/rk3399/clock.c | 121 +++++++++++++++++++++++++++
src/soc/rockchip/rk3399/include/soc/clock.h | 2 +
2 files changed, 123 insertions(+)

Upstream: review.coreboot.org

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