rockchip/rk3399: Change PLL configuration to match Linux kernel

Hardware / Coreboot - Julius Werner [chromium.org] - 17 November 2016 10:59 UTC

The Kevin project has been too smooth and boring for our tastes in the last last few weeks, so we've decided to stir the pot a little bit and reshuffle all our PLL settings at the last minute. The new settings match exactly what the Linux kernel expects on boot, so it doesn't need to reinitialize anything and risk a glitch.

Naturally, changing PLL rates will affect child clocks, so this patch changes vop_aclk (192MHz -> 200MHz, 400MHz in the kernel), pmu_pclk (99MHz -> 96.57MHz) and i2c0_src (198MHz -> 338MHz, leading to an effective I2C0 change 399193Hz -> 398584Hz).

BRANCH=gru BUG=chrome-os-partner:59139 TEST=Booted Kevin, sanity checking display and beep. Instrumented rockchip_rk3399_pll_set_params() in the kernel and confirmed that GPLL, PPLL and CPLL do not get reinitialized anymore (with additional kernel patch to ignore frac divider when it's not used). Also confirmed that /sys/kernel/debug/clk_summary now shows pclk_pmu_src 96571429 because the kernel doesn't even bother to reinitialize the divisor.

Change-Id: Ib44d872a7b7f177fb2e60ccc6992f888835365eb

8e42bd1 rockchip/rk3399: Change PLL configuration to match Linux kernel
src/soc/rockchip/common/i2c.c | 11 ++++---
src/soc/rockchip/rk3399/clock.c | 43 +++++++++++++--------------
src/soc/rockchip/rk3399/display.c | 2 +-
src/soc/rockchip/rk3399/include/soc/clock.h | 6 ++--
4 files changed, 32 insertions(+), 30 deletions(-)

Upstream: review.coreboot.org

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