soc/intel/quark: Enable Serial Port

Hardware / Coreboot - Lee Leahy [intel.com] - 9 February 2016 09:20 UTC

Add the code to enable debug serial output using HSUART1:

- Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
- Note that the BIST value is always zero as validated in esram_init.inc
- The initial TSC value is currently not saved!

Testing on Galileo:
- Edit the src/mainboard/intel/galileo/Makefile.inc file
- Add "select ADD_FSP_PDAT_FILE"
- Add "select ADD_FSP_RAW_BIN"
- Add "select ADD_RMU_FILE"
- Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
- Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE
- Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
- Testing is successful if serial output is present on HSUART1 at 115200 baud, 8-bit, no parity

Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0

87df8d0 soc/intel/quark: Enable Serial Port
src/soc/intel/quark/Kconfig | 42 +++++++++++++++++++++++++
src/soc/intel/quark/Makefile.inc | 4 +++
src/soc/intel/quark/include/soc/iomap.h | 27 ++++++++++++++++
src/soc/intel/quark/include/soc/pci_devs.h | 26 +++++++++++++++
src/soc/intel/quark/include/soc/romstage.h | 29 +++++++++++++++++
src/soc/intel/quark/romstage/Makefile.inc | 3 ++
src/soc/intel/quark/romstage/cache_as_ram.inc | 41 +++++++++++++++++++++++-
src/soc/intel/quark/romstage/romstage.c | 27 ++++++++++++++++
src/soc/intel/quark/romstage/uart.c | 42 +++++++++++++++++++++++++
src/soc/intel/quark/tsc_freq.c | 36 +++++++++++++++++++++
src/soc/intel/quark/uart.c | 40 +++++++++++++++++++++++
11 files changed, 316 insertions(+), 1 deletion(-)

Upstream: review.coreboot.org

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