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soc/intel/skylake: Add C entry bootblock support

Hardware / Coreboot - Subrata Banik [intel.com] - 27 July 2016 22:15 UTC

List of activity performing in this patch- early PCH programming- early SA programming- early CPU programming- mainborad early gpio programming for UART and SPI- car setup- move chipset programming from verstage to post console

BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x34

Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143

e4a8537 soc/intel/skylake: Add C entry bootblock support
src/soc/intel/common/Makefile.inc | 3 ++
src/soc/intel/skylake/Kconfig | 13 +----
src/soc/intel/skylake/Makefile.inc | 18 ++++---
src/soc/intel/skylake/bootblock/bootblock.c | 27 +++++++++-
src/soc/intel/skylake/bootblock/cpu.c | 66 ++---------------------
src/soc/intel/skylake/bootblock/pch.c | 18 ++++++-
src/soc/intel/skylake/bootblock/systemagent.c | 4 +-
src/soc/intel/skylake/bootblock/uart.c | 71 +++++++++++++++++++++++++
src/soc/intel/skylake/include/soc/bootblock.h | 28 ++++++++++
src/soc/intel/skylake/include/soc/romstage.h | 1 -
src/soc/intel/skylake/romstage/Makefile.inc | 16 +++---
src/soc/intel/skylake/romstage/pch.c | 3 +-
src/soc/intel/skylake/romstage/romstage.c | 18 -------
src/soc/intel/skylake/romstage/uart.c | 70 ------------------------
14 files changed, 171 insertions(+), 185 deletions(-)

Upstream: review.coreboot.org